Error detecting device, error detection method and control system

ABSTRACT

An error detecting device enables proper detection of an occurrence of a data error in a register. The error detecting device for detecting an occurrence of a data error in a register for holding input data with reception of a write permission comprises an operation circuit for performing a prescribed operation with each data output from a plurality of registers, a comparison register for storing data for comparison, a write unit for writing data obtained through the operation in the operation circuit into the comparison register in accordance with the timing of write permission by the write permission signal and a comparator for comparing the data for comparison stored in the comparison register with the data obtained through the operation in the operation circuit so as to detect garbled data in the registers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an error detecting device, an errordetection method and a control system and, more particularly, to anerror detecting device, an error detection method and a control systemfor detecting an occurrence of a data error (garbled data) in a registerwhich temporarily stores data to be calculated or a calculated result.

2. Description of the Relevant Art

Garbled data is sometimes caused in a register by a power failure ornoise. If the processing is continued as usual in spite of theoccurrence of garbled data in the register, there is a possibility thatthe electronic equipment itself may be damaged. Therefore, it isextremely important to detect the occurrence of garbled data in theregister.

For that reason, hitherto, various kinds of methods for detectinggarbled data in a register have been proposed (e.g. see thebelow-mentioned Patent Document 1). FIG. 6 is a block diagramschematically showing the principal part of a conventional errordetecting device for detecting garbled data in a register. Theconventional error detecting device comprises a state hold register 1for holding input data, an inverter circuit (NOT circuit) 2 forinverting and outputting the input data, a reference register 3 forholding the data from the inverter circuit 2, an inverter circuit 4 forinverting and outputting the data from the state hold register 1, anNAND circuit 5 for receiving the data from the inverter circuit 4 andthe data from the reference register 3, and operating and outputting a‘negated AND’, and an EX-OR circuit 6 for receiving the data from theinverter circuit 4 and the data from the reference register 3, andoperating and outputting an ‘exclusive-OR’ (that is, deciding thecorrectness of the data held in the state hold register 1 and outputtingan error flag).

A data control signal is a signal for permitting to write data into thestate hold register 1 and the reference register 3. The state holdregister 1 holds the input data when receiving the data control signalwhich permits the writing of data. The reference register 3 holds thedata from the inverter circuit 2 (the inverted data of the input data)when receiving the data control signal.

A detecting operation of an occurrence of a data error performed with adata holding operation in this error detecting device is describedbelow. First, a case of no occurrence of a data error is described. Whenan input signal data into the state hold register 1 is ‘0’, and thestate hold register 1 and the reference register 3 receive a datacontrol signal of ‘1’, the state hold register 1 holds the data ‘0’ andthe reference register 3 holds the data ‘1’.

In this situation, the data ‘1’ from the inverter circuit 4 and the data‘1’ from the reference register 3 are output to the NAND circuit 5 andthe EX-OR circuit 6. Accordingly, the data ‘0’ (the same as the dataheld in the state hold register 1) is output from the NAND circuit 5,while the data ‘0’ is output from the EX-OR circuit 6 as an error flag.When a data error occurs, the error flag turns ‘1’.

Next, a case of an occurrence of a data error is described. When thedata held in the state hold register 1 is transformed from ‘0’ to ‘1’due to an instantaneous power interruption and the like, the data ‘0’from the inverter circuit 4 and the data ‘1’ from the reference register3 are output to the EX-OR circuit 6, leading to outputting of the data‘1’ from the EX-OR circuit 6 as an error flag. Thus, the occurrence of adata error can be detected.

However, in this conventional error detecting device, in order to detectan occurrence of a data error in one register (state hold register 1),another register (reference register 3) is required, that is, adouble-register construction is needed, resulting in a great increase incost. In addition, when the scale of a digital circuit is huge, thedouble-register construction is extremely difficult to realize withconsideration of arrangement space and the like.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2004-13196

SUMMARY OF THE INVENTION

The present invention was accomplished in order to solve the aboveproblem, and it is an object of the present invention to provide anerror detecting device, an error detection method and a control system,whereby an occurrence of a data error in a register can be appropriatelydetected without double-register construction.

In order to achieve the above object, an error detecting deviceaccording to a first aspect of the present invention is characterized byan error detecting device for detecting an occurrence of a data error ina register for holding input data with reception of a write permission,the error detecting device comprising an operation unit for performing aprescribed operation with each data output from a plurality of registersto be examined, a memory for storing data for comparison, a write unitfor writing data obtained by the operation unit into the memory inaccordance with the timing of the write permission, and a comparisonunit for comparing the data for comparison stored in the memory with thedata obtained by the operation unit.

When the error detecting device according to the first aspect of thepresent invention is used, the prescribed operation (e.g. an operationfor finding the sum of all data) is performed with each data output fromthe plurality of registers to be examined, and data obtained throughthis operation is written into the memory as the data for comparison inaccordance with the timing of the write permission. And the data forcomparison stored in the memory and the data obtained by the operationunit (the prescribed operation) are compared with each other.

It is natural that the data to be obtained through the prescribedoperation should be influenced and be changed by a change of the data tobe output from the registers (that is, the data to be held in theregisters).

In a normal operating condition, the data to be held in the registerschanges only in a case where the registers received the writepermission. Accordingly, in a normal operating condition, the data to beobtained through the prescribed operation also changes only in a casewhere the registers received the write permission.

The writing of the data obtained through the prescribed operation intothe memory is conducted in accordance with the timing of the writepermission. That is, the writing of the data obtained through theprescribed operation into the memory is conducted, as described below,when the registers receive the write permission, the data to be held inthe registers changes, and as a result of being influenced by thechange, the data to be obtained through the prescribed operationchanges.

When the registers receive the write permission:

the data to be held in the registers (the data to be output from theregisters) changes;

the data to be obtained through the prescribed operation is influencedby the change and is changed; and then,

the data obtained through the prescribed operation is written into thememory as the data for comparison.

Thus, during normal operation of the registers, the latest data to beobtained through the prescribed operation is always stored in thememory. Therefore, during normal operation of the registers, the datastored in the memory (the data for comparison) and the data to beobtained through the prescribed operation are always the same.

On the other hand, when the data to be held in the registers is changedby a power failure or noise (garbled data), and the data to be obtainedthrough the prescribed operation is influenced by the change and ischanged, the data to be stored in the memory is not updated. That isbecause the garbled data has nothing to do with the write permission.Therefore, when the data to be held in the registers is changed by apower failure or noise, a difference is caused between the data (thedata for comparison) stored in the memory and the data to be obtainedthrough the prescribed operation.

Thus, during normal operation of the registers, the data (the data forcomparison) stored in the memory and the data to be obtained through theprescribed operation are the same. However, when the data to be held inthe registers is changed by a power failure or noise, a difference iscaused between the data (the data for comparison) stored in the memoryand the data to be obtained through the prescribed operation. Therefore,by comparing the data for comparison with the data obtained by theoperation unit, an occurrence of a data error in the registers can bedetected.

An error detecting device according to a second aspect of the presentinvention is characterized by the operation unit which performs alogical operation in the error detecting device according to the firstaspect of the present invention.

When the error detecting device according to the second aspect of thepresent invention is used, a logical operation is performed in theoperation unit, and so values to be obtained through the prescribedoperation are limited to two values of ‘1’ and ‘0’. As a result, theoperation unit can be made of a comparatively simple circuit. Here, asthe logical operation, AND, OR and EX-OR are exemplified.

An error detecting device according to a third aspect of the presentinvention is characterized by the operation unit which performs anarithmetic operation in the error detecting device according to thefirst or second aspect of the present invention.

As described above, when the prescribed operation is limited to alogical operation, values to be obtained through the prescribedoperation are limited to two values of ‘1’ and ‘0’. Therefore, even if adata error occurs, for example, there is a possibility that theoccurrence of the data error may not be reflected on a result to beobtained through the prescribed operation, resulting in failure todetect the data error.

When the error detecting device according to the third aspect of thepresent invention is used, an arithmetic operation (e.g. addition,subscription, multiplication and division) is performed, and so valuesto be obtained through the prescribed operation are not limited to thetwo values of ‘1’ and ‘0’. As a result, the occurrence of a data errorcan be more properly detected. Here, the prescribed operation can be notonly addition, subscription, multiplication and division, but also acombination with a logical operation. Or in the case of division, notquotient but remainder can be used in the operation.

An error detecting device according to a fourth aspect of the presentinvention is characterized by the write unit which writes the dataobtained by the operation unit into the memory with a predetermined timedelay after the timing of the write permission in any of the errordetecting devices according to the first to third aspects of the presentinvention.

When the data obtained by the operation unit is written into the memoryat the same time as the timing of the write permission, that is, withoutany delay after the timing, there is a possibility that not the updatedresulting data but the resulting data not yet updated may be writteninto the memory.

When the error detecting device according to the fourth aspect of thepresent invention is used, the data obtained by the operation unit iswritten into the memory not at the same time as the timing of the writepermission but with a predetermined time delay (e.g. 1 clock delay)after the timing. Thus, it is possible to prevent the writing ofresulting data not yet updated into the memory.

An error detecting device according to a fifth aspect of the presentinvention is characterized by the registers which are scattered on anintegrated circuit in any of the error detecting devices according tothe first to fourth aspects of the present invention.

When the error detecting device according to the fifth aspect of thepresent invention is used, an occurrence of a data error caused by apower failure or noise can be detected across the integrated circuitsince the registers are scattered on the integrated circuit (such as anLSI). Here, if the registers are evenly spaced across the integratedcircuit, the occurrence of a data error can be detected more properly.

An error detecting device according to a sixth aspect of the presentinvention is characterized by further comprising a plurality ofmemories, wherein the data obtained by the operation unit is writteninto every memory in any of the error detecting devices according to thefirst to fifth aspects of the present invention.

In the error detecting device according to the first aspect of thepresent invention, the writing of the data obtained through theprescribed operation into the memory is conducted in accordance with thetiming of the write permission. Therefore, wrong data is not writteninto the memory.

However, when a data error is caused by a power failure or noise atabout the same time as the normal timing of writing, there is apossibility that wrong data may be written into the memory and that theoccurrence of the data error may not be detected.

When the error detecting device according to the sixth aspect of thepresent invention is used, a plurality of memories are arranged, and thedata obtained by the operation unit is written into each of thememories. As a result, even if wrong data was written into any one ofthe memories, the memory/memories into which correct data was writtenexists/exist, leading to detection of the occurrence of a data error.

An error detecting device according to a seventh aspect of the presentinvention is characterized by a plurality of memories and the registersto be examined which are divided into groups, further comprising theoperation unit arranged in every group, wherein data obtained by eachoperation unit is separately written into each memory in any of theerror detecting devices according to the first to fourth aspects of thepresent invention.

When the error detecting device according to the seventh aspect of thepresent invention is used, a plurality of memories are arranged, and thedata obtained by the operation unit is written into each of thememories. As a result, even if wrong data was written into any one ofthe memories, the memory/memories into which correct data was writtenexists/exist, leading to detection of the occurrence of a data error.

Furthermore, the registers to be examined are divided into groups, theoperation unit is arranged in each of the groups, and data obtained byeach of the operation units is written into each of the memories,respectively. As a result, the number of the registers to be dealt withby one of the operation units can be reduced, leading to a simplecircuit configuration or simple interconnections.

An error detecting device according to an eighth aspect of the presentinvention is characterized by the registers which are scattered on anintegrated circuit and are divided into groups based on their locationsin the error detecting device according to the seventh aspect of thepresent invention.

When the error detecting device according to the eighth aspect of thepresent invention is used, an occurrence of a data error caused by apower failure or noise can be detected across the integrated circuitsince the registers are scattered on the integrated circuit (such as anLSI). In addition, since the registers are divided into groups based ontheir locations (closer registers are grouped), the length ofinterconnections which are required for realizing the prescribedoperation can be shortened, leading to a simple circuit configuration.Here, when the registers are evenly spaced across the integratedcircuit, the occurrence of a data error can be detected more properly.

An error detection method according to a first aspect of the presentinvention is characterized by an error detection method for detecting anoccurrence of a data error in a register for holding input data withreception of a write permission, the error detection method comprising astep of performing a prescribed operation with each data output from aplurality of registers to be examined, a step of writing data obtainedthrough the operation into a memory for storing data for comparison inaccordance with the timing of the write permission, and a step ofcomparing the data for comparison stored in the memory with the dataobtained through the operation.

In the error detection method according to the first aspect of thepresent invention, the prescribed operation (e.g. an operation forfinding the sum of all data) is performed with each data output from theplurality of registers to be examined, and the data obtained through theoperation is written into the memory as the data for comparison inaccordance with the timing of the write permission. And the data forcomparison stored in the memory and the data obtained by the operationunit (the prescribed operation) are compared with each other.

During normal operation of the registers, the data (the data forcomparison) stored in the memory and the data to be obtained through theprescribed operation are the same. However, when the data to be held inthe registers is changed by a power failure or noise, a difference iscaused between the data (the data for comparison) stored in the memoryand the data to be obtained through the prescribed operation. Therefore,by comparing the data for comparison with the data obtained by theoperation unit, the occurrence of a data error in the registers can bedetected.

A control system according to a first aspect of the present invention ischaracterized by a control system in which any of the error detectingdevices according to the first to eighth aspects of the presentinvention is adopted, comprising a plurality of registers for holdingdata obtained from a millimeter wave radar, a control unit forconducting control based on the data held in the registers, an operationunit for performing a prescribed operation with each data output fromthe plurality of registers, a memory for storing data for comparison, awrite unit for writing data obtained by the operation unit into thememory in accordance with the timing of the write permission and acomparison unit for comparing the data for comparison stored in thememory with the data obtained by the operation unit.

A control system according to a second aspect of the present inventionis characterized by a control system in which the error detection methodaccording to the first aspect of the present invention is adopted,comprising a plurality of registers for holding data obtained from amillimeter wave radar, a control unit for conducting control based onthe data held in the registers, an operation unit for performing aprescribed operation with each data output from the plurality ofregisters, a memory for storing data for comparison, a write unit forwriting the data obtained by the operation unit into the memory inaccordance with the timing of the write permission and a comparison unitfor comparing the data for comparison stored in the memory with the dataobtained by the operation unit.

As a system in which data obtained from a millimeter wave radar is used,an adaptive cruise control system for keeping a distance from a vehicleahead is exemplified. The adaptive cruise control system is effectivefor avoiding a collision with a vehicle ahead. In order to avoid acollision properly, the use of data including no garbled data isextremely important. In other words, with the use of data including anerror, a high degree of accuracy in control on a distance between carscannot be expected.

In the control system according to the first or second aspect of thepresent invention, it is possible to detect an occurrence of a dataerror in the register which holds data obtained from the millimeter waveradar. Thus, even if the data obtained from the millimeter wave radar isused, it is possible to properly conduct control with high accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing the principal part of anerror detecting device according to a first embodiment of the presentinvention;

FIG. 2 is a block diagram schematically showing the principal part of anerror detecting device according to a second embodiment;

FIG. 3 is a block diagram schematically showing the principal part of anerror detecting device according to a third embodiment;

FIG. 4 is an illustration of an error detecting device according toanother embodiment;

FIG. 5 is a block diagram schematically showing the principal part of anadaptive cruise control system in which an error detecting device or anerror detection method according to a first example is adopted; and

FIG. 6 is a block diagram schematically showing the principal part of aconventional error detecting device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the error detecting device and the errordetection method according to the present invention are described belowby reference to the Figures noted above. FIG. 1 is a block diagramschematically showing the principal part of an error detecting deviceaccording to a first embodiment (or a device in which an error detectionmethod according to the first embodiment is adopted). Reference numeral11 in FIG. 1 represents a data bus, to which registers 12-14 to beexamined are connected. To the registers 12-14, write permission signalsW₁₂-W₁₄ for permitting the writing of data on the data bus 11 are input,respectively. When the write permission signal W₁₂ turns a high level of‘1’, the data on the data bus 11 is held in the register 12. Similarly,when the write permission signal W₁₃ or W₁₄ turns a high level of ‘1’,the data on the data bus 11 is held in the register 13 or 14.

The write permission signals W₁₂ and W₁₃ are output to an OR circuit 15for operating and outputting an ‘OR’. Resulting data Q₁₅ in the ORcircuit 15 and the write permission signal W₁₄ are output to an ORcircuit 16 for operating and outputting an ‘OR’. Resulting data Q₁₆ inthe OR circuit 16 is output to a write delay circuit 17. Accordingly,when at least one of the write permission signals W₁₂-W₁₄ is a highlevel of ‘1’, a signal of high-level ‘1’ is input to the write delaycircuit 17. If at least one of the input signals to the OR circuit 15 or16 becomes a high level of ‘1’, the output signal therefrom becomes ahigh level of ‘1’.

The registers 12-14 output data Q₁₂-Q₁₄ held therein to the outside. Thedata Q₁₂ output from the register 12 and the data Q₁₃ output from theregister 13 are output to an operation circuit 18. Resulting data Q₁₈ inthe operation circuit 18 and the data Q₁₄ output from the register 14are output to an operation circuit 19. Resulting data Q₁₉ in theoperation circuit 19 is output to both a comparison register 20 forholding comparison data and a comparator 21.

As the operation circuits 18 and 19, logical operation circuits such asan AND circuit, an OR circuit and an EX-OR circuit, and arithmeticoperation circuits such as an addition (ADD) circuit, a subscription(SUB) circuit, a multiplication (MUL) circuit and a division (DIV)circuit can be adopted.

To the comparison register 20, a write permission signal W₂₀ forpermitting the writing of the resulting data Q₁₉ output from theoperation circuit 19 is input from the write delay circuit 17. When thewrite permission signal W₂₀ turns a high level of ‘1’, the resultingdata Q₁₉ is held in the comparison register 20. And from the comparisonregister 20, comparison data Q₂₀ held therein is output to thecomparator 21.

After receiving a signal of high-level ‘1’ from the OR circuit 16, thewrite delay circuit 17 outputs the write permission signal W₂₀ ofhigh-level ‘1’ to the comparison register 20 with one clock delay. Asdescribed above, when at least one of the write permission signalsW₁₂-W₁₄ is a high level of ‘1’, a signal of high-level ‘1’ is input tothe write delay circuit 17.

Accordingly, when data is written into one of the registers 12-14 (i.e.the resulting data Q₁₉ to be obtained through the operations in theoperation circuits 18 and 19 changes), a signal of high-level ‘1’ isoutput to the comparison register 20 and the updated resulting data Q₁₉is held in the comparison register 20 as the comparison data Q₂₀. Thus,in the comparison register 20, the latest resulting data Q₁₉ is alwaysstored (except in the cases where a data error was caused by a powerfailure or noise).

The delay processing is conducted in the write delay circuit 17 in orderto prevent not the updated resulting data Q₁₉ but the not-yet-updatedresulting data Q₁₉ from being held in the comparison register 20 as thecomparison data Q₂₀ when a signal of high-level ‘1’ is output to thecomparison register 20 as soon as a signal of high-level ‘1’ is receivedfrom the OR circuit 16.

To the comparator 21, the comparison data Q₂₀ output from the comparisonregister 20 and the resulting data Q₁₉ are input. The comparator 21compares the comparison data Q₂₀ with the resulting data Q₁₉. When thecomparison result is true (here, when the both are the same), comparisonresult data Q₂₁ of low-level ‘0’ (an error flag) is output. On the otherhand, when the comparison result is false, the comparison result dataQ₂₁ of high-level ‘1’ is output.

As described above, in the comparison register 20, the latest resultingdata Q₁₉ is always stored. Therefore, in a normal operating condition,the comparison data Q₂₀ and the resulting data Q₁₉ are inevitably thesame, and from the comparator 21, the comparison result data Q₂₁ oflow-level ‘0’ is output.

On the other hand, when at least one of the data Q₁₂-Q₁₄ held in theregisters 12-14 is changed by a power failure or noise, the resultingdata Q₁₉ is influenced by that and is changed. However, in this case,since the write permission signals W₁₂-W₁₄ are not a high level of ‘1’,the write permission signal W₂₀ of high-level ‘1’ is not input to thecomparison register 20 and the comparison data Q₂₀ is not updated. As aresult, a difference is caused between the comparison data Q₂₀ and theresulting data Q₁₉, leading to an output of the comparison result dataQ₂₁ of high-level ‘1’ from the comparator 21.

Moreover, to the registers 12-14 and the comparison register 20, a resetsignal is input. When receiving the reset signal, the registers 12-14and the comparison register 20 perform reset processing. Therefore, forexample, when an occurrence of a data error was detected, the registers12-14 and the comparison register 20 are returned to their initialstates by providing the reset signal to the registers 12-14 and thecomparison register 20. And then, by making at least one of the writepermission signals W₁₂-W₁₄ a high level of ‘1’ so as to produce thewrite permission signal W₂₀, the value in the comparison register 20 canbe made normal and the comparison result data Q₂₁ (error flag) can bemade ‘0’. The reason why such write processing is conducted is becausefor normal initialization, the write processing is required at leastonce after reset since the reset signal often gets noise.

When the error detecting device according to the first embodiment isused, the comparison data Q₂₀ held in the comparison register 20 and theresulting data Q₁₉ are the same during normal operation of the registers12-14. However, when at least one of the data Q₁₂-Q₁₄ held in theregisters 12-14 is changed by a power failure or noise, a difference iscaused between the comparison data Q₂₀ held in the comparison register20 and the resulting data Q₁₉. As a result, by comparing the comparisondata Q₂₀ with the resulting data Q₁₉, the occurrence of a data error inthe registers 12-14 can be detected.

Here, concerning the error detecting device according to the firstembodiment, a case where there are three registers to be examined hasbeen described. But the error detecting device according to the presentinvention is not limited to the case of three registers to be examined,and it is needles to say that two registers or four or more registerscan be arranged.

In addition, the registers to be examined had better be scattered on anintegrated circuit (e.g. an LSI). If the registers to be examined arescattered on the integrated circuit, it is possible to detect anoccurrence of a data error caused by a power failure or noise across theintegrated circuit. It is far better if the registers to be examined areevenly spaced on the integrated circuit. Furthermore, in an errordetecting device according to another embodiment, registers which areplaced where a power failure or noise is particularly likely to occurmay be preferentially examined.

FIG. 2 is a block diagram schematically showing the principal part of anerror detecting device according to a second embodiment (or a device inwhich an error detection method according to the second embodiment isadopted). Here, the same components as those of the error detectingdevice shown in FIG. 1 are similarly marked. Reference numeral 31 inFIG. 2 represents a write delay circuit, to which resulting data Q₁₆ inan OR circuit 16 for operating and outputting an ‘OR’ is input.Accordingly, when at least one of write permission signals W₁₂-W₁₄ is ahigh level of ‘1’, a signal of high-level ‘1’ is input to the writedelay circuit 31.

The registers 12-14 output data Q₁₂-Q₁₄ held therein to the outside. Thedata Q₁₂ output from the register 12 and the data Q₁₃ output from theregister 13 are output to an operation circuit 18. Resulting data Q₁₈ inthe operation circuit 18 and the data Q₁₄ output from the register 14are output to an operation circuit 19. Resulting data Q₁₉ in theoperation circuit 19 is output to comparison registers 20 and 32 forholding comparison data and to comparators 21 and 33.

To the comparison register 20, a write permission signal W₂₀ forpermitting the writing of the resulting data Q₁₉ output from theoperation circuit 19 is input from the write delay circuit 31. When thewrite permission signal W₂₀ becomes a high level of ‘1’, the resultingdata Q₁₉ is held in the comparison register 20. And from the comparisonregister 20, comparison data Q₂₀ held therein is output to thecomparator 21.

And to the comparison register 32, a write permission signal W₃₂ forpermitting the writing of the resulting data Q₁₉ output from theoperation circuit 19 is input from the write delay circuit 31. When thewrite permission signal W₃₂ becomes a high level of ‘1’, the resultingdata Q₁₉ is held in the comparison register 32. And from the comparisonregister 32, comparison data Q₃₂ held therein is output to thecomparator 33. Here, as described in more detail below, the timing ofwriting the resulting data Q₁₉ is different between the comparisonregisters 20 and 32.

After receiving a signal of high-level ‘1’ from the OR circuit 16, thewrite delay circuit 31 outputs the write permission signal W₂₀ ofhigh-level ‘1’ to the comparison register 20 with one clock delay andoutputs the write permission signal W₃₂ of high-level ‘1’ to thecomparison register 32 with another one clock delay. As described above,when at least one of the write permission signals W₁₂-W₁₄ is a highlevel of ‘1’, a signal of high-level ‘1’ is input to the write delaycircuit 31.

As a result, when the writing of data into any one of the registers12-14 is conducted (i.e. the resulting data Q₁₉ to be obtained throughthe operations in the operation circuits 18 and 19 is changed), a signalof high-level ‘1’ is output to the comparison register 20 (32) and theupdated resulting data Q₁₉ is held in the comparison register 20 (32).Thus, in the comparison register 20 (32), the latest resulting data Q₁₉is always stored (except in the cases where a data error was caused by apower failure or noise).

Here, the delay processing is conducted in the write delay circuit 31 inorder to prevent not the updated resulting data Q₁₉ but the resultingdata Q₁₉ not yet updated from being held as the comparison data Q₂₀(Q₃₂) in the comparison register 20 (32) when a signal of high-level ‘1’is output to the comparison register 20 (32) as soon as a signal ofhigh-level ‘1’ is received from the OR circuit 16.

To the comparator 21 (33), the comparison data Q₂₀ (Q₃₂) output from thecomparison register 20 (32) and the resulting data Q₁₉ are input. Thecomparator 21 (33) compares the comparison data Q₂₀ (Q₃₂) with theresulting data Q₁₉. When the comparison result is true (here, when theboth are the same), comparison result data Q₂₁ (Q₃₃) of low-level ‘0’ isoutput, while the comparison result data Q₂₁ (Q₃₃) of high-level ‘1’ isoutput when the comparison result is false.

As described above, the latest resulting data Q₁₉ is always stored inthe comparison register 20 (32). Therefore, in a normal operatingcondition, the comparison data Q₂₀ (Q₃₂) and the resulting data Q₁₉ areinevitably the same, and the comparison result data Q₂₁ (Q₃₃) oflow-level ‘0’ is output from the comparator 21 (33).

On the other hand, if at least one of the data Q₁₂-Q₁₄ held in theregisters 12-14 is changed by a power failure or noise, the resultingdata Q₁₉ is influenced by that and is changed. However, in this case,since the write permission signals W₁₂-W₁₄ are not a high level of ‘1’,the write permission signal W₂₀ (W₃₂) of high-level ‘1’ is not input tothe comparison register 20 (32) and the comparison data Q₂₀ (Q₃₂) is notupdated.

As a result, a difference is caused between the comparison data Q₂₀(Q₃₂) and the resulting data Q₁₉, and from the comparator 21 (33), thecomparison result data Q₂₁ (Q₃₃) of high-level ‘1’ is output.

The comparison result data Q₂₁ from the comparator 21 and the comparisonresult data Q₃₃ from the comparator 33 are output to an OR circuit 34for operating and outputting an ‘OR’, and resulting data in the ORcircuit 34 is output as an error flag. An output signal from the ORcircuit 34 becomes a high level of ‘1’ when at least one of the inputsignals thereto is a high level of ‘1’.

To the registers 12-14 and the comparison registers 20 and 32, a resetsignal is input. When the registers 12-14 and the comparison registers20 and 32 receive the reset signal, reset processing is conducted.Therefore, for example, when an occurrence of a data error was detected,by providing the reset signal to the registers 12-14 and the comparisonregisters 20 and 32, and conducting the write processing at least once,the registers 12-14 and the comparison registers 20 and 32 can bereturned to their normal initial states.

When the error detecting device according to the second embodiment isused, during normal operation of the registers 12-14, the comparisondata Q₂₀ (Q₃₂) held in the comparison register 20 (32) and the resultingdata Q₁₉ are the same. However, when at least one of the data Q₁₂-Q₁₄held in the registers 12-14 is changed by a power failure or noise, adifference is caused between the comparison data Q₂₀ (Q₃₂) held in thecomparison register 20 (32) and the resulting data Q₁₉. As a result, bycomparing the comparison data Q₂₀ (Q₃₂) with the resulting data Q₁₉, theoccurrence of a data error in the registers 12-14 can be detected.

By the way, when a data error is caused by a power failure or noise atabout the same time as the normal timing of writing, there is apossibility that wrong data may be written into the comparison registerand that the comparison data may be wrong data. However, pluralcomparison registers, the comparison registers 20 and 32, are arranged,and the writing of data is conducted with different timing from eachother. Therefore, even if wrong data was written into either of thecomparison registers 20 and 32, there is a comparison register intowhich correct data was written. As a result, the occurrence of a dataerror can be detected.

Here, concerning the error detecting device according to the secondembodiment, the case where two comparison registers 20 and 32 arearranged as resisters for comparison has been described above, but inthe error detecting device according to the present invention, thenumber of comparison registers is not limited to two. Three or morecomparison registers can be arranged.

FIG. 3 is a block diagram schematically showing the principal part of anerror detecting device according to a third embodiment (or a device inwhich an error detection method according to the third embodiment isadopted). Reference numeral 41 in FIG. 3 represents an error detectingcircuit, to which a data bus 11 is connected, and write permissionsignals W₁₂-W₁₄ and a reset signal are input. Here, the error detectingcircuit 41 has the same construction as the error detecting device shownin FIG. 1. Data Q₁₂-Q₁₄ held in registers 12-14 and comparison resultdata Q₂₁ showing a comparison result in a comparator 21 are output tothe outside.

An error detecting circuit 141 has the same construction as the errordetecting circuit 41, comprising registers 112-114, OR circuits (notshown), a write delay circuit (not shown), operation circuits (notshown), a comparison register 120 and a comparator 121. To the errordetecting circuit 141, the data bus 11 is connected similarly to theerror detecting circuit 41, and write permission signals W₁₁₂-W₁₁₄ forpermitting the writing of data into the registers 112-114 and a resetsignal are input. And data Q₁₁₂-Q₁₁₄ held in the registers 112-114 andcomparison result data Q₁₂₁ showing a comparison result in a comparator121 are output to the outside.

The comparison result data Q₂₁ from the error detecting circuit 41(comparator 21) and the comparison result data Q₁₂₁ from the errordetecting circuit 141 (comparator 121) are output to an OR circuit 42for operating and outputting an ‘OR’, and resulting data in the ORcircuit 42 is output as an error flag. The output signal from the ORcircuit 42 becomes a high level of ‘1’ when at least one of the inputsignals thereto is a high level of ‘1’.

When the error detecting device according to the third embodiment isused, the occurrence of a data error can be detected in the errordetecting circuits 41 and 141 each. Therefore, when garbling of dataoccurs in the registers 112-114 though there is no garbled data in theregisters 12-14, the occurrence of a data error can be detected in theerror detecting circuit 141. Conversely, when garbling of data occurs inthe registers 12-14 though there is no garbled data in the registers112-114, the occurrence of a data error can be detected in the errordetecting circuit 41. As a result, the occurrence of a data error can bemore certainly detected.

Moreover, there are plural comparison registers, comparison registers 20and 120. Therefore, even if wrong data was written into either of thecomparison registers 20 and 120, there is a comparison register intowhich correct data was written, resulting in detection of the occurrenceof a data error.

Here, concerning the error detecting device according to the thirdembodiment, the case wherein two error detecting circuits 41 and 141 arearranged as error detecting circuits has been described above, but inthe error detecting device according to the present invention, thenumber of error detecting circuits is not limited to two. Three or moreerror detecting circuits can be arranged.

Moreover, each error detecting circuit had better be scattered on anintegrated circuit (e.g. an LSI). For example, when error detectingcircuits 41, 141 and 141A-141G are scattered on an LSI 43 as shown inFIG. 4, an occurrence of a data error caused by a power failure or noisecan be detected across the LSI 43. It is far better if the errordetecting circuits are evenly spaced across the integrated circuit. Inan error detecting device according to another embodiment, errordetecting circuits may be preferentially arranged where a power failureor noise is likely to occur.

In addition, by dividing the registers 12-14 and 112-114 to be examinedinto groups based on their locations (i.e. grouping closer registers),the length of interconnections for connecting each circuit can beshortened, resulting in a simple circuit configuration.

In the error detecting devices according to the first to thirdembodiments, as shown in FIGS. 1 and 2, the data Q₁₂-Q₁₄ output from theregisters 12-14 are operated in the operation circuits 18 and 19, andthe resulting data Q₁₉ is output to the comparison register 20 and thecomparator 21. But in an error detecting device according to anotherembodiment, the number of operation circuits may be reduced. Aprescribed operation may be performed on data Q₁₂-Q₁₄ in one operationcircuit, and so the resulting data Q₁₉, is output to a comparisonregister 20 and a comparator 21.

When the prescribed operation is performed, it is desirable that arelation between the data Q₁₂-Q₁₄ and the resulting data Q₁₉, that if atleast one value of the data Q₁₂-Q₁₄ is changed, the value of theresulting data Q₁₉, changes together should be satisfied.

When this relation is satisfied, the resulting data Q₁₉ changes,regardless of whether the values of the data Q₁₂-Q₁₄ are changed bynormal writing or by a data error.

As an operation which satisfies such relation, for example, anexclusive-OR operation is performed on any two values of the dataQ₁₂-Q₁₄ at every bit and an exclusive-OR operation on a result of theoperation and the remaining one value is performed at every bit. As aconcrete circuit configuration, a circuit configuration including anexclusive-OR operation circuit is exemplified.

This is just one example, and if it is an operation satisfying theabove-described relation, other operation methods or other circuitconfigurations can be adopted. As the other circuit configurations,logical circuits such as AND, OR, NOT, NA-ND, NMOSNAND, CMOSNAND, NORand NMOSNOR, arithmetic circuits such as XOR, HALFADDER, FULLADDER,ADDER, SUB, MULTIPLIER, HALFADDERfordivid, FULLADDERfordivid andDIVIDER, and other function operation processing are exemplified. Acombination of them can also be adopted.

Here, in the case of the prescribed operation being performed, it isdesirable that the above-described relation be satisfied, but 100%satisfaction is not needed. For example, in the case of a hash functionbeing adopted as the prescribed operation, there may be a case where theresulting data Q₁₉, does not change together with the change of the dataQ₁₂-Q₁₄. But if the probability of such case is slight, the object ofthe present invention to detect garbled data in a register with highaccuracy is achieved.

Concerning the error detecting devices according to the above-describedembodiments, as shown in FIGS. 1 and 2, the case where there are threeregisters to be examined has been described. But the number of registersto be examined is not limited to three. In another embodiment, aconstruction for detecting garbled data in two registers or four or moreregisters may be adopted.

EXAMPLE 1

FIG. 5 is a block diagram schematically showing the principal part of anadaptive cruise control system (equivalent to a control system accordingto the present invention) where an error detecting device or an errordetection method according to Example 1 is adopted. Reference numeral 51in FIG. 5 represents a radar sensor unit, comprising a radar antenna 52,a scanning mechanism 53 and a signal processing circuit 54. As the radarsensor unit 51, a millimeter wave radar is exemplified.

The signal processing circuit 54 comprises a scanning angle control unit55, a radar signal processing unit 56 and a target recognition unit 57.The radar signal processing unit 56 performs FET processing on areflection signal from the radar antenna 52, detects a power spectrum,calculates a distance from a target (a vehicle ahead) and a relativespeed, and sends data showing the distance from the target and therelative speed to the target recognition unit 57.

An adaptive cruise control ECU (electronic control unit) 58 controls analarm 62, a brake 63, a throttle 64 and associated parts when receivingsignals from a steering sensor 59, a yaw rate sensor 60, a speed sensor61 and the target recognition unit 57.

The target recognition unit 57 provides a scanning angle to the scanningangle control unit 55 and decides a target to be used for the controlbased on the distance from the target and the relative speed receivedfrom the radar signal processing unit 56, and vehicle information suchas a steering angle, a yaw rate and a speed received from the adaptivecruise control ECU 58, and sends information about the target to theadaptive cruise control ECU 58.

In the case of a radar of a fixed type, the scanning angle control unit55 controls the scanning angle in driving on curves, while it controlsthe range of scanning in the case of a radar of a scanning type. Thescanning mechanism 53 sequentially launches beams at given angles forscanning when receiving a control signal from the scanning angle controlunit 55.

In the radar signal processing unit 56, the target recognition unit 57and the adaptive cruise control ECU 58, the error detecting device orthe error detection method according to the present invention isadopted. Therefore, data errors in registers (storage circuits fortemporarily storing data) on ICs such as microcomputers used in theradar signal processing unit 56, the target recognition unit 57 and theadaptive cruise control ECU 58 can be detected.

1. An error detecting device for detecting an occurrence of a data errorin a register for holding input data with reception of a writepermission, the error detecting device comprising: an operation unit forperforming a prescribed operation with each data output from a pluralityof registers to be examined; a memory for storing data for comparison; awrite unit for writing data obtained by the operation unit into thememory in accordance with the timing of the write permission; and acomparison unit for comparing the data for comparison stored in thememory with the data obtained by the operation unit.
 2. An errordetecting device according to claim 1, wherein the operation unitperforms a logical operation.
 3. An error detecting device according toclaim 1, wherein the operation unit performs an arithmetic operation. 4.An error detecting device according to claim 1, wherein the write unitwrites the data obtained by the operation unit into the memory with apredetermined time delay after the timing of the write permission.
 5. Anerror detecting device according to claim 1, wherein the registers arescattered on an integrated circuit.
 6. An error detecting deviceaccording to claim 1, further comprising: a plurality of memories,wherein the data obtained by the operation unit is written into everymemory.
 7. An error detecting device according to claim 1, wherein aplurality of memories are arranged and the registers to be examined aredivided into groups, further comprising: the operation unit arranged inevery group, wherein data obtained by each operation unit is separatelywritten into each memory.
 8. An error detecting device according toclaim 7, wherein the registers are scattered on an integrated circuitand are divided into groups based on locations of the registers.
 9. Anerror detection method for detecting an occurrence of a data error in aregister for holding input data with reception of a write permission,the error detection method comprising: a step of performing a prescribedoperation with each data output from a plurality of registers to beexamined; a step of writing data obtained through the operation into amemory for storing data for comparison in accordance with the timing ofthe write permission; and a step of comparing the data for comparisonstored in the memory with the data obtained through the operation.
 10. Acontrol system in which the error detecting device according to claim 1is adopted, comprising: a plurality of registers for holding dataobtained from a millimeter wave radar; a control unit for conductingcontrol based on the data held in the registers; an operation unit forperforming a prescribed operation with each data output from theplurality of registers; a memory for storing data for comparison; awrite unit for writing data obtained by the operation unit into thememory in accordance with the timing of the write permission; and acomparison unit for comparing the data for comparison stored in thememory with the data obtained by the operation unit.
 11. A controlsystem in which the error detection method according to claim 9 isadopted, comprising: a plurality of registers for holding data obtainedfrom a millimeter wave radar; a control unit for conducting controlbased on the data held in the registers; an operation unit forperforming a prescribed operation with each data output from theplurality of registers; a memory for storing data for comparison; awrite unit for writing the data obtained by the operation unit into thememory in accordance with the timing of the write permission; and acomparison unit for comparing the data for comparison stored in thememory with the data obtained by the operation unit.